I agree with Erik....And when a CPLD or FPGA is reacting strangely on my boards I will go back to the design and add visibility and/or monitoring of internal nodes to spare I/O pins. (I never commit a programmable part into a design without a certain percentage of spare I/O pins). There are certain types of testing you can do on the real target hardware via these test pins using an oscilloscope and/or a logic analyzer that cannot be done effectively with a simulator. As a matter of fact, on several projects I wasted more time on attempting to setup the test bench to simulate a CPLD design than it took to initially design the part and then debug it in the target circuit.
Michael Karas