Hallo George,

I think, what Jez focused is the reason for failure.

But be aware, there's a trap in your application. Your circuit could suffer from bus contention! Assume, you address your RAM, but still have port 3.5 line at low level. Then, 74HCT540 is enabled and some outputs may try to make high level while port 2 lines try to make low level, with the result that 74HCT540 outputs and pull-down NMOS transistors of port 2 outputs are short circuited! The resulting big current flowing from Vcc through PMOS of 74HCT540, further through NMOS of port 2 output to ground will destroy one or both outputs!! So, be very careful when testing software. P3.5 must never have low level, when RAM is accessed!
But even with this care, there's a certain probability for occuring bus contention, even if software is designed correctly. Think about, why you use a watchdog! If you assume, that mcu can run ill, some time, then you must also assume, that P3.5 line erroneously is at low level, while accessing RAM. So, you should always have some hardware guarantee, that bus contention is reliably prohibited, equally which actual 'code' is running.

If have noticed, that RAM is all the time enabled. This may result in drastical increase of supply current of application. Have you analyzed this? (May be, that your RAM device is different to others, which I know.)

Another question, why didn't you connect reset output of MAX 1232 directly to reset input pin of mcu? I would make here a direct connection. Additionally, a pull-up of about 4k7...10k from this line to Vcc can help to guarantee high level even at Vcc voltages below about 2V.

By the way, your schematic looks nice!

Good luck,
Kai