hi raghu,


your tight loop works EA is dropped to zero. Theoritically what intels manual states that a Latch input value is scanned at first phase S6P1 and changes at S6P2 last cycle of the instruction, and it actually appears at the port pin at S1P1 of next instruction that was doubt in my mind that this may affect the duty cycle. now i realise that when ever it may be cpl bit comes in to effect. the time it will take affect again, is same which means in turn that off time will always be equal to the off time.



abhishek