Hi all,
I have managed to lock up three chips now, because of a stupid bug in the Atmel SPI ISP system.

To quote Equinox, who have been very helpful indeed (and are only 20km from me)

Description
The AT89S device requires that the ‘SCK’ pin is driven ‘LOW’ by the external ISP programmer before the device is placed into RESET mode. This means that the SCK pin must be asserted ‘LOW’ by the programmer while the processor is actually executing ‘user firmware’. If the ‘user firmware’ happens to write a logic ‘0’ to the SCK pin before the external programmer has
had chance to drive the pin LOW, then the device will never re-enter ‘Serial Programming Mode’. It appears that the SPI shift register inside the AT89S device receives at least one erroneous edge on the SCK pin (hdue to an
internal design problem) thereby getting out of synchronisation. As there is no way of the programmer detecting when it is in sync or not, it is impossible to get the AT89S device into programming mode. This explains why the device programmed correctly the fist time, but locks up on subsequent attempts. I used a home brewed programmer and thought that was the problem, but after buying the Equinox in desparation today I now have found out why.

My system starts to use the SPI bus as the device comes out of reset, so fast that the Equinox ISP can't get control of the interface in time. NOW I know that the device needs to be handled with extreme care and I need a startup delay of one second before my code uses the SPI bus. I can unlock the parts with a parallel programmer, but I haven't built an adapter yet.

Thanks to Equinox, I now know that the Temic part is better anyway ( and it has EEPROM on board )

Steve