sram address bus config

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07/21/03 13:49
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#51055 - sram address bus config

In a standard 32K*8 sram chip, are the address pins in the correct order to input binary? for example, if i wanted to access the first byte of data, would i set up the address lines like this?

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

0 0 0 0 0 0 0 0 0 0 0 0 0 1

and for the second byte like this:

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

0 0 0 0 0 0 0 0 0 0 0 0 1 0

and so on, or do the address lines go the other way around, a14 being at the end etc?

Are the data lines the same also, do they go D7 to D0 descending the same as the address lines?

Thanks, Gordon

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Topic Author Date
sram address bus config              01/01/70 00:00
   RE: sram address bus config              01/01/70 00:00
   RE: sram address bus config              01/01/70 00:00
      RE: sram address bus config              01/01/70 00:00
         RE: sram address bus config              01/01/70 00:00
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Topic	Author	Date
*sram address bus config*		01/01/70 00:00
RE: sram address bus config		01/01/70 00:00
RE: sram address bus config		01/01/70 00:00
RE: sram address bus config		01/01/70 00:00
RE: sram address bus config		01/01/70 00:00
RE: sram address bus config		01/01/70 00:00