You don't have to believe me, just do a few experiments. The problem I had with page mode is I could not READ from eeprom once the first write to the column latches occured, no matter what other SFRs were changed, only committing the columns to eeprom would allow reading. So, for the RD2, at the chip revision level I was using, the only way to even use the eeprom after writing to one byte in the column latch was to write the latch.

Since I never disable XRAM mapping, I also conclude that the EEPROM bit has priority.