After the peripheral chip drives the data bus and asserts the READY signal (indicating to the 8051 that data are ready), the peripheral chip will drive the data bus for only a few clock cycles. Thus, the interrupt latency would be too long to capture the data.

If the peripheral chip would wait for an acknolwedgement before removing data from the bus, then an ISR-based approach would work. But, in this case the peripheral drives the bus for a fixed period of time.

I guess what I really need is an 8051 that will stretch its memory cycle until it sees the READY signal (similar to the MC68000's /DTACK signal).