Hallo Raghunathan,

you could try the following circuit:





Working with very large data hold periods presents a problem with classic analog peak detectors: Circuits, which guarantee very low drop rates, are not capable of handling fast rising and short lasting 'peak signals' at input. So, in many cases two stage designs can be necessary. Schematic above shows such a two stage design.

Assume we want a capacitor have storing (hold) a peak signal. In a typical peak detector circuit five different influences will then work against us:

1. Natural internal discharge of capacitor itself:
For 2µ2 MKT capacitor made of Polyester foil (WIMA) datasheet tells, that at 25°C internal discharge is like having a resistor of 30GOhm having connected across terminals. Supposing a stored voltage of 10V, an internal discharging current of about 330pA will thenflow. Using an MKP capacitor, which is made of Polypropylen internal discharging current is about ten times smaller.

2. Leakage current through charging diode:
Leakage current of 1N4151 at 25°C and some Volts of reverse voltage is about 5nA. If reverse voltage is limited to very low values almost reaching zero, leakage current can be drastically decreased! This is done in the second stage peak detector.

3. Input bias current of OPamp:
LF353 at 25°C shows up to about 75pA, typically. It's worth to note, that many FET-OPamps show a drastical increase of input bias current up to several nanoampere, when common mode voltage is increased to more than 5V. So, when not wanting to use LF353 be very carefully in choosing an adequate equivalent. LF355 and LF356 can also be used, but NOT TL05X, e.g.!

4. Leakage current through turned-off discharging transistor:
At room temperature (25°C) and some Volts of collector emitter voltage leakage current of BC546B is less than 200pA, typically. Provided, that base emitter voltage is zero! So, we must control RESET pin of circuit by an output, which is able to present almost 0V. Output of 74HCMOS gate is recommended.

5. Leakage current through PCB:
PCB material does not show absolute insulation. Resistivity is highly dependend on manufacturer, etc. Also, dirt on surface of PCB will additionally present a problem. So, hold capacitor becomes charged and discharged from potentials of direct environment!
It's absolutely essential to clean the PCB after soldering, but it's even more essential to use the concept of 'guarding'. Guarding minimizes PCB caused leakage currents, by completely surrounding sensitive points of PCB by a guard ring, which is connected to same potential. In our case, guard ring is connected to inverting input of OPamp, which shows same potential as sensitive terminal of hold capacitor.


We conclude: With careful design a total leakage current of less than 1nA is possible, at second stage. At first stage less than about 5nA is possible. But keep in mind, that all parameters discussed above are typicals and are valid only at room temperature. In your actual design exchange of certain components might be necessary, or a pre matching of components. But that's the price of use of cheap and available OPamps, transistors and diodes.

With circuit shown above a drop rate of about 500µV/sec can be achieved, means a voltage drop of 10mV after 20sec. Peak signal at input must be present for at least 20µsec.

A word to reset circuitry: BC546B shows very low leakage current, when turned-off, but cannot discharge hold capacitor totally, when turned-on. Voltage at hold capacitor will not fall below some tens of milivolt.
And, when transistors are turned-on, 1k resistors are in parallel to hold capacitors, so, when input voltage is not zero, hold capacitors cannot be discharged, but will follow input signal. But his is NO disadvantage, because after reset phase is finished, hold capacitor will be charged to actual input voltage anyway!


Good luck,
Kai