hi,
just a remark: original poster says:
And all the PWM signals runs at different frequencies
Hans, in your example all pwmregs are incremented with same speed, so their duty cycles are different but the frequences are same.

As for me, so I would preffered a way has been suggested by David: use one timer with defined time-quanta and provide three registers` sets: counter and Zero and One durations. In this case, the code looks like below

PWM1_COUNTER	DATA	0xXX			; pwm counter
PWM1_LOW	DATA	0xXX			; low duration reload value
PWM1_HIGH	DATA	0xXX			; high duration reload value

; timer isr
T0_ISR:
	MOV	TH0,#T0_SCALE_H			; reload value for timed-quanta
	PUSH	ACC

	DJNZ	PWM1_COUNTER,T0_ISR_PWM2	; wait loop
; time to do
	CPL	Px.x				; toggle output
	JB	Px.x,T0_ISR_PWM1_H
	MOV	PWM1_COUNTER,PWM1_LOW		; low duration
	JMP	T0_ISR_PWM2
T0_ISR_PWM1_H:
	MOV	PWM1_COUNTER,PWM1_HIGH		; high duration
; next PWM
T0_ISR_PWM2:
; next PWMs here

There are some notes here:
- if frequence and duty cycle are constants then high and low duration registers may be rejected and just two constant numbers are used instead;
- if software needs with more accurate timings (in example above, PWM2/3/4 etc have different latency due some variable jumps take place before) then it should divide time quanta on number of PWMs and maintain only one PWM inside ISR each time.

cu