Hallo Yogesh,

we have very often discussed this topic here in the past. I would recommend you to make a search in this forum.

1. Think about that rest circuitry will show low level, when Vcc is removed. So, when your SRAM only has low active chip enable lines (/CE) how do you disable the chip? I often used a SRAM which also contained an active high chip enable line (CE).

2. Voltage at inputs of SRAM must show exactly 0V, otherwise input stages are partially turned-on. But due to leakage current flowing into or out of inputs, circuitry connected to inputs will be floated, often resulting in a biasing of protection or parasitic substrate diodes. The only way to circumvent this is to connect a pull down resistor from each input to 0V. Something arround 100kOhm is approriate.

3. Very low supply current will only be observed with certain types of SRAMS. You need an LL-type, being optimized for very low data retention supply current. Just to use a standard CMOS RAM can result in a drastically increased supply current.

4. Supply voltage of SRAM in data retention mode should be much lower than 3.6V. Have a look into datasheet to find out what minimal supply voltage for data retention mode is recommended.


Kai