Well, do you see any reason to use such scheme?

No. But original developers of microcontrollers only had NMOS and bipolar transistors. High quality MOSFETs with low drain source voltage weren't available.
Think about ULN2004. It's a Darlington array, including base resistors. May be they thought about such stuff, when stating that 'a port bit might be used to drive the base of a transistor'?
Well, anyhow what you connect to port pins, transistors with base resistors, Darlingtons with or without base resistors, there's always the possibility, that due to rather high ohmic source impedance of port pin (weak pull-up pFET3!), voltage at port pin goes dangerously low. Think about a port voltage of 2.4V, while a current of about 100µA is delivered. Wouldn't it be much more advantageous always to read the latch instead of pin?

There are many features of performance, which make not necessarily sense, when having a short look. But if you consider other possible conditions of micro, they do make sense, suddenly. Think about power-saving modes of micro, e.g.: If weak pull-up pFET3 couldn't be turned-off when driving pin voltage low, power supply current would rapidely increase! Maximum logical 1-to-0 transition current is specified to be smaller than -650...-750µA per port pin (Port 1,2,3). This current is caused by weak pull-up pFET3. If this weak pull-up couldn't be turned-off, more than 20mA could flow, when all 24 port lines are driven low. But fortunately, pFET3 is turned-off and only maximal -50µA will flow per port pin, caused by very weak pull-up pFET2. That makes about only 1.2mA additionally, when the 24 port lines are driven low.

Kai