I'm using the 813F1 in couple of my projects and it is a neat solution.
Just some precautions
- older 813s has some problem in the silicon i.e., the macro cells will load by the low level and not by edge triggering. Hence, code produced by the present version of SW will not work 'cause they produce edge triggered mode only. The work around is to use older version i.e Ver 5.1 which allows you to choose level or edge trigger. This problem is corrected in the newer silicons with 'A' suffix. I dont think this problem exist in 9xx chips.

- If you are planning to use JTAG pins for gen IO also, pls program a pin or a node as JTAG enable. In the former case,
you don't need the uC intervention to program and the later case you need the
uC or some means to enable the node. In either case you have to isolate the IO during programming. There is an application note (AN 054) on this at their website.

Richard wrote
>>sharing the JTAG port with GP I/O and >>managed to ruin a device
Pls correct me if I am wrong. You can not program 'cause the JTAG port is disabled. If so, rewrite the code considering JTAG enable mentioned above and connect the 'ruined' device in circuit with a uC. Access and enable the JTAG enable register in the CSIOP array and program thro' JTAG.

Once, the JTAG is disabled only way to reclaim is to use the above method or use a special programmer.