Hello,

I'm struggling with the following problem .
I have to count the amount of pulses from an external clocksignal. The Start/stop of counting is triggered by an external signal on /int0(gate). I configured timer 0 as a 16 bit counter in gating mode.Means that as long as /int0 is high and the counter is started,the counter will increase his value on a falling edge of the clocksignal.
On the falling edge of /INT0 the counter stops counting and an interrupt occur .In the ISR the counted values are handled.As a test case i used a 1 MHz clk signal on T0 and a 400usec puls on /int0.
Value of the counter should be something around 400

Gate |-------------|
____|..................|__400us ext. sign. on /int0

..........|-|..|-|..|-|..|-|
clk.__|.|_|.|_|.|_|.|__1Mhz ext. sign on T0

Problem that i have is that my counting values are not correct and not alway's the same.Please find a part of the initialisation code below where timer0 and timer1 are configured in the same way .
I'm using a 80C51F120 from cygnal running at 50 Mhz.
Cygnal users can find a simular post on the cygnal forum.

I configure the timer as follow:

void Timer_Init()
{
SFRPAGE = TIMER01_PAGE;
CKCON = 0x00;// reset clock control register no influence , external clock used.
TL0= 0x00; // Reset counter values for counter 0 and 1
TL1= 0x00;
TH0= 0x00;
TH1= 0x00;
TCON= 0x05; // interrupt falling edge triggered
TMOD= 0xDD; // gated 16 bit counters. counting
TCON|=0x50; // Start counters
}
void Interrupts_Init()
{
SFRPAGE= TIMER01_PAGE;
IE0=0;
IE1=0;
IP= 0x05; //INT0 and /INT1 High priority
IE= 0x85; //Enable all interrupts= /INT0 and /INT1
}

After resetting and initialising some things in the main program
I'm just waiting for interrupts.


The ISR looks like:

void IRQ0_ISR (void) interrupt 0
{
EX0=0; //Disable interrupt site 1, back enabled in main
SFRPAGE=TIMER01_PAGE;
TR0=0; //stop timer 0 , again started in main
if(TF0) //Check overflow flag
{
SITE1_L=0xFF; //Values on overflow will be FF
SITE1_H=0xFF;
TF0=0; //Clear overflow flag
}
else
{
SITE1_L=TL0;
SITE1_H=TH0;
SITE1|=(int)SITE1_H;
SITE1=_irol_(SITE1,8);
SITE1|=(int)SITE1_L;
TL0=0;
TL1=0;
}
}


Any advice on this ?

Regards,
Luc