Thanks Steve,

I searched the forum and found many answers, Trying to sort it out.

Mehmet.

I am not able to under stand what you say how you solved it.

Raghunath & Erik

Thanks for your suggestions I had bought Agilent HCTL 2020 it a nice chicp that all the headache of encoder reqading but I am facing a new problem while reading the chip I had studied the datasheets and implemented the algo routing mentioned in it but I am able to read only one byte ie both the times while reading hi byte and ll byte the reading is same which I asume that chip is not latching its data while hi byte is being read for the first pulse it is 1 in hi byte and 1 in lo byte thus showing the reading ..257..514..1028 ...65535. vice versa.

here is the simple routine that I had implemented.

HCTL MCU

D0…..D7 ------ P1.0…….P1.7

CLK ALE
SEL P3.0 (low for reading hi byte and high for reading low byte on data pins)
OE P3.1 ( low to enable data to latch on output)
RST P3.2 (low to make reset)

RD2020:

CLR OE_HCTL ; SELECT OUTPUT ENABLE LATCH
CLR SEL_HCTL ; SELECT HIGH BYTE OF HCTL-2020
MOV A,P1 ; ENC_DATA IN HI BYTE
MOV ENC_HI_BYTE,A ; STORE IN INTERNAL RAM

SETB SEL_HCTL ; SELECT LOW BYTE OF HCTL-2000
MOV A,P1 ; ENC_DATA IN LO BYTE
MOV ENC_LO_BYTE,A ; STORE IN INTERNAL RAM
SETB OE_HCTL ; CLEAR ENABLE OUTPUT LATCH
RET

The datasheet says after making SEL and OE low the next CLK falling edge will inhibit the data from being tranfered to out puts and the hi byte data is latched in next making SEL Hi the next falling edge on CLK low byte data will be latched. I have been the only thing I found if CLK is not latching the data.

Please do let me know the ALE pin connected to CLK is ok or suggest me how do I sort my problem.

Thanks every one for help

Regards.......Manjeet