Sorry, it's quite difficult for me to explain the problem here, in english, which is "not my first language".

I would like to place the program here:
DI is the converted data from the ADC, and AD is the multiplexer address. CLK is the clock line.

CLR CLK
CLR CS

MOV C,DI
MOV 20H.7,C
MOV C,MUX.4
MOV AD,C
SETB CLK
CLR CLK

MOV C,DI
MOV 20H.6,C
MOV C,MUX.3
MOV AD,C
SETB CLK
CLR CLK

This is only two clock period, which I receive the data on the negative level of CLK, and place mux address before the rising edge of CLK.

After the CS line (chip select) is brought low, the mux address is entered on the rising edge of CLK. Converted data is shown on the data line, on the falling edge of CLK. So the CLK line has to be low before the whole process start, but I didn't CLR the line. So the whole transfer process is offset.

Stanley