ok,

So when i keep the DIOR pin low the data
is helt on the databus right?

and when the pin is made high again the
databus is high-impedance. (im right?)

Ive checked the IDE datasheets again, and they didn't mention anything about that the CS lines should be asserted/negated after the DIOW/DIOW is negated :-<

To test if i got it right i send the
media eject command..

; device head reg
cs = 0x02
da = 0x06
databus 0..7 0b11100000
set diow ; ^ ^
clr diow ; 1 2
;1 = LBA , CHS
;2 = MASTER, SLAVE (right?)

; send command this case media eject
cs = 0x02
da = 0x07
databus 0..7 0xef ;media eject
set diow
clr diow

But as usual (murphy's law) nothing happends...

sigh.