??? 08/05/04 15:15 Read: times |
#75487 - RE: Memory mapped I/O hassle Responding to: ???'s previous message |
Hi Raghu,
Have you checked the list file to see if the bits actually end up at the addresses you expect? My Raisonance assembler lets me do this: DSEG AT 20H IOBYTE_1: DS 1 10HPMOTOR BIT IOBYTE_1.0 SOL_LOAD BIT IOBYTE_1.1 .... .... SOL_REV BIT IOBYTE_1.7Which will correctly overlay the bits for certain. If your ASEM_51 supports this syntax, I would use it if I were you. Best regards, Rob. |
Topic | Author | Date |
Memory mapped I/O hassle | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
Problem defenition - Erik | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
Automatic up I/O update - Russell | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
Syntax - Anders, Rob, Charles | 01/01/70 00:00 | |
RE: Syntax - Anders, Rob, Charles | 01/01/70 00:00 | |
Problem solved - Russell | 01/01/70 00:00 | |
RE: Syntax - Anders, Rob, Charles | 01/01/70 00:00 | |
RE: Syntax - Anders, Rob, Charles | 01/01/70 00:00 | |
RE: Memory mapped I/O hassle | 01/01/70 00:00 | |
Thread can close happily![]() | 01/01/70 00:00 |