Prahlad,

I'm a bit confused. Didn't you read my last reply? What I suggested there looks like that:





Following your explaination about how your signal current is produced, signal current will not show any dc component. Only 50Hz terms and lots of harmonics. This means that you can provide AC coupling in the intergrator section, allowing you to prevent all problems resulting from offset voltages of involved operational amplifiers! The only you have to do is to choose C1 in such a way, that its impedance at all frequencies of interest (>= 50Hz) is much SMALLER than R4.

How works C1?
Input offset voltage of TL052A is +-0.8mV maximum at 25°C. If the first OPamp shows a gain of 'G', then at its output an offset voltage of +-0.8mV x G will be present.
Further assume that also second OPamp shows an input offset voltage. Then, potential of inverting input of second OPamp would be slightly shifted by exact this amount of offset voltage, which is less than +-0.8mV. The result is, that across the series circuit of C1 and R4 the difference of both offset voltages (output offset voltage of first OPamp and input offset voltage of second) drops. As consequence a current will flow which charges C1 to this potential difference. And if once C1 is totally charged, offset voltage will not have any further effect on this integrator!!

An example:
Assume that ouptut offset voltage of first OPamp is 5.0mV and that potential at inverting input of second OPamp is 0.4mV. Then C1 is charged to 5.0mV - 0.4mV = 4.6mV. After C1 is charged, no further DC current will flow through R4, means offset voltage will not have any influence on integrator circuit.
As no further DC current will flow through R4, there woun't be any further DC current flowing through R5 either, and at output of integrator the same potential will be present as at inverting input, namely 0.4mV. This is the error your integrator fabricates due to offset voltage.
Keep in mind, that this error voltage of 0.4mV will be constant. No rise to infinity, as it will be the case with DC coupled integrators...

In the simplified schematic you will find another component, which was added, R5. What is its purpose?
As OPamps suffer from unavoidable input offset voltage, they are also prone to show some unavoidable input bias current. With TL052A this input bias current is 200pA maximum at 25°C. Although very small, input bias current would also cause the output of integrator drift to infinity, if not taken into consideration. This is done here by the help of R5. Input bias current will cause a constant voltage drop across R5. No rise to infinity!

How works R5?
Input bias current flows through inverting input terminal and searches for a current path to 0V. This can also be the output of an operational amplifier. In our case input bias current will flow via R5 to output of second OPamp. Of course, this produces a voltage drop across R5 causing another error voltage at output of integrator.
Take care that R5 is choosen in such a way, that its impedance is much BIGGER than impedance of C3, at all frequencies of interest (<= 50Hz). Then influence of R5 on performance of integrator will be negligible!

An example:
As an FET OPamp is used in the above schematic input bias current is very small, in our case less than 200pA. R5 should be choosen very high. R5 is only limited by the eroneous voltage drop of input bias current. As a rule of thumb, eroneous voltage drop should equall input offset voltage. Then error terms of offset voltage and input current are equal. This yields: R5 <= 0.8mV / 200pA = 4MOhm.

This gives a total maximum error voltage at output of integrator of less than 0.8mV + 0.8mV = 1.6mV, which is only 0.016% of 10V, or by other words, which would represent 12bit resolution. If this error is too high, then choose a better OPamp.

You see, with this simple modification of integrator, neither a chopper is needed, nor any forced periodical discharge of integration capacitor...

Kai