Is it ok to use this supervisor with micros having internal WDT which emit RESET.

No! Such a micro would have a PMOS FET which clamps the reset pin to Vcc. If at the same time a supervisor chip, connected to reset pin, emits low level by the help of its NMOS FET, then a short circuit exists! Even if this will not result in destruction (but what is very likely to happen!), level at reset pin will be far away from true high level.

By the way: The P89C51RD2 HAS the option to activate the reset pin!!! So, be very careful. If WDOUT pin in WDTC register is set, internal watchdog will activate reset pin for 32 clock periods, means an internal PMOS FET will clamp reset pin to Vcc.

If this emitting of reset avtive level by the internal watchdog is wished, or cannot be disabled, then supervisor chip must treat reset pin very carefully. A scheme like the following could then be used, for instance:



But this circuit (and all others!) has a certain disadvantage: As no NMOS FET is allowed to pull down potential at reset pin, input will see a very high source impedance, whenever reset isn't invoked! This resistance can be decreased somewhat, of course, by paralleling an external pull-down resistor, as shown in the schematic. But nevertheless the source impedance seen by the reset input will be allways in the 1...10kOhm range. Not a good idea for a high speed microcontroller circuit...

From the above schematic it should also be clear, that a RC power-on-reset circuit will not work either. Why? Because the internal PMOS FET will not be able to discharge external C within 32 clock periods! Assume a clock frequency of 11MHz, then 32 clock periods would yield 2.9µsec. Now assume that internal PMOS FET has a turn-on resistance of 50 Ohm. Then, an external 10µF capacitor would only loose 0.6% of its charge! Means, potential at reset pin cannot rise to high level!!


Michael wrote:
During the crucial time that the Vcc is transitioning from GND to +5 volts the reset generator chip itself will provide a predictable output condition even at the instant the Vcc is at say 0.96 volts. The CMOS inverters output state at this same voltage will not be predictable. As a matter of fact the inverter output most likely looks like it is in a tri-state condition!!

Yes, this is true. For such a case an errata sheet from Intel recommended the use of a pull-up resistor connected directly from reset pin to Vcc. This would eliminate the tristate perfomance.
Maxim uses the same trick, by the way, to guarantee that reset signal is active even when Vcc falls below 1V. This can be seen in datasheet of MAX705 e.g.

Kai