I know its off topic but it might possibly save someone a lot of frustration and swearing.
I have just spent an entire day debugging a friends new board which he couldn’t get working because the high speed logic he had put into a cpld refused to work despite the fact that he had he said simulated it in Modelsim and it had all worked.
So when using Modelsim to verify custom logic in programmable logic devices remember that simply compiling the logic and testbench only verifies the fact that the logic design is correct ,it does not verify that the logic will work with any given logic device at a given clock speed.
The only way to verify that the logic will work with your choosen device at the required clock speed is
1, Compile the HDL and testbench if appropriate.
2, Run the testbench to verify the logical operation of the design ,at this stage Modelsim is using Virtual logic gates with implied propagation and setup and hold times of zero.This is called a behavioural model.
3, If the design works synthesise the logic using your vendor’s synthesis tool, fit the logic using your vendor’s logic fitter to your chosen device.
4, Take the netlist and SDF files generated by the logic fitter and compile them using Modelsim,The netlist is functionally equivalent to the hdl but is composed entirely of logic blocks found in your chosen device,the sdf file contains the timing constraints for the logic blocks.Modelsim will attach the timing constraints from the sdf file to the logic gates in the netlist.
5, Run the testbench against the netlist. This is known as a functional model,if you crank the clock up too high it will fail due to timing constraint violations. Only if the functional model passes the testbench can you be sure that the actual device will work. If it fails rinse and repeat.

Its not difficult to do and if my friend had done this instead of just doing a behavioural simulation it would have saved him a lot of time and money.