Jez Smith wrote:

"I never trust the figures given by static analysis,"

Why not? I don't particularly trust the numbers spit out by the synthesis tools, but the place-and-route timing numbers are VERY reliable. I would imagine that if Xilinx and Altera and all of the ASIC vendors didn't think that static timing analysis wasn't reliable, they wouldn't go through much effort to improve those tools.

"but we both use VHDL it has much more interesting ways to shoot yourself in the foot."

Neither language will prevent you from making logic errors, but at least VHDL's strong typing and verbosity mean that the compiler will catch a lot of mistakes. Verilog happily compiles most of what you throw at it.

--a