Jez,

"The only way to verify that the logic will work with your choosen device at the required clock speed is [to run a back-annotated timing simulation using the same test bench]."

Did you friend bother to set timing constraints in the fitter software, and did he look at the results of the static timing analysis?

Unless your design is freaky -- asynchronous weirdness, combinatorial latches, etc -- the static timing analysis tells you whether your design will work at your desired clock frequency.

I don't deny that it's a good idea to run a post-fit timing simulation, but I've never had a problem with a design not working when the timing analysis says that I win.

Having said all of that, the REAL problem is that too many people write awful Verilog. I've seen LOTS of cases where someone's Verilog simulated in some interesting ("it looked correct in the waveform display!") way, but it was written such that the synthesis tool accepted it but the output was NOT what the designer intended. Needless to say, the design didn't work. Yes, Verilog gives you a lot of rope, and too many engineers end up hanging. Verilog is truly a "minute to learn, a lifetime to master."

I could also go into my rant about how most test benches are wholly inadequate for anything more complex than a 22V10 PAL design, but now that's REALLY off-topic. Suffice it to say that I spend MUCH more time writing my test benches than I do writing the RTL for the chip.

-a