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???
09/21/04 15:19
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#77847 - RE: problem with SPI & MAX6662 (at89s8252)
Responding to: ???'s previous message
hi,

When i wire both lines i always recive 0x00.

oops, that`s very strange. Are you sure that you connected together exactly MISO+MOSI but not another line to MISO? In fact, when you write 0xFF to SPDR then only 1s should be shifted out from MOSI. Sure, it does not explain why 0x00 is received then.

So we start from beginning. First of all, show how do you initialize SPI. I ask it because after reset, by default SPI is configured as CPOL=0, SPHA=1. It means that SCK of the master device is low when not transmitting (suitable for MAX6662). And it means that data is valid from master at falling edge of clock. Last rule is not compatible with MAX6662 which requires valid data at rising edge.
So first of all, check: do you reset CPHA=0 before communications?

Regards,
Oleg

List of 12 messages in thread
TopicAuthorDate
problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
   RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
      RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
         RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
      RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
         RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
            RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
               RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
                  RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
                     RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
                        RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      
                           RE: problem with SPI & MAX6662 (at89s8252)            01/01/70 00:00      

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