I wanted to enter this in the shiny new hardware code library ut the link didnt work :(
Anyway...

---vhdl code to generate the simplest and therefore the fastest practical binary up
---counter structure in a cpld/fpga.In most synthesis tools the generic counter
--- macro is a trade off between size and speed and will not generate wide/fast counters easily
---

---The counter consists of an array of T-type flip flops and AND gates.
---Most modern cplds can implement an AND gate upto 48 bits wide therefore counters upto
---48 bits long need only one layer of decode logic.Clock rates of 250 Mhz for a 32 bit
--- counter are achievable in a xilinx 95xl series cpld.

---Inputs
---clk clock in
---reset_n active low asyncronous reset

---Outputs
---q N bit wide counter output


library ieee;
use ieee.std_logic_1164.all;

entity tff is
port(clk :in std_logic;
t :in std_logic;
clear :in std_logic;
q :inout std_logic);
end tff;

architecture rtl of tff is
begin
process(clear, clk)
begin
if clear = '0' then
q <= '0';
elsif rising_edge(clk) then
if t = '1' then
q <= not q;
else
null;
end if;
end if;
end process;
end rtl;



library ieee;
use ieee.std_logic_1164.all;

entity bigcntr is
generic(size : positive := 32); ---counter width
port(clk : in std_logic;
reset_n : in std_logic;
q : inout std_logic_vector((size-1) downto 0));
end bigcntr;

architecture rtl of bigcntr is

component tff is
port(clk :in std_logic;
t :in std_logic;
clear :in std_logic;
q :inout std_logic);
end component;

signal tin : std_logic_vector((size-1) downto 0);

begin

genttf : for i in (size-1) downto 0 generate
ttype : tff port map (clk, tin(i), reset_n, q(i));
end generate;

genand : for i in 0 to (size-1) generate
t0 : if i = 0 generate
tin(i) <= '1';
end generate;
t1_size : if i > 0 generate
tin(i) <= q(i-1) and tin(i-1);
end generate;
end generate;

end rtl;