Jez Smith wrote:



Don't forget that all current FPGAs have very efficient carry chains, and the synthesis tools will use these to generate proper fast counters. This is one place where CPLDs lose to FPGAs.

For example, I coded up a simple 32-bit clearable counter as follows (using Verilog):

module counter
    (input wire clk,
     input wire rst_l,
     input wire clear,
     output reg [31:0] q);

    always @(posedge clk or negedge rst_l) begin : CountMe

	if (~rst_l) begin
	    q <= 32'd0;
	end else begin
	    if (clear)
		q <= 32'd0;
	    else
		q <= q + 32'd1;
	end // else: !if(~rst_l)
    end // block: CountMe
endmodule // counter

I targetted the Altera Cyclone FPGA family. After synthesis and place and route, the timing analyzer tells me that this counter can run at 377.22 MHz. This is with the default synthesis and place-and-route settings, and a single timing constraint of 250 MHz for the clock. I'm sure I'd get similar results using a Xilinx Spartan 3 FPGA.

I went back and targetted a MAX7128AE part and it topped out at 126 MHz. A Lattice Mach4000V part topped out at 181 MHz. So, while CPLDs have the advantage of fan-in compared to FPGAs, they don't have the architectural optimizations (like carry chains) that are common in FPGAs.

If you choose the part that better fits the application, you can avoid jumping through hoops.

To bring this on topic, I bet I could whip up a wicked-fast 8052 in a modern FPGA without too much trouble!

-a