Thanks for reply. Might be i was unable to put my question correctly. I have read most of this document. i want to design 8051 in verilog.
suppose instruction is 1 cycle 2 bytes. In first stage ( 2 clks) opcode is read, in 4th stage 2nd byte is read. I want to know what is done in 2,3 5 and 6 stage or in each clock from 1 to 12. i think you got my question now. Once again thanks for your previous reply. It was helpful.
Regards
Nitin