Opcode is fetched in states 1 and 4.
Interrupt flags are latched during state 5.
Port latches are sampled by their output buffers only during state 1. During state 2 the output buffer holds the value it saw during the previous state. In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch during state 6 and will appear valid at state 1 of next machine cycle. If the change requires a 0-to-1 transition in ports 1,2 or 3, an additional pullup is turned on during state 1 of the cycle in which the transisiton occurs.
External inputs are sampled during state 5 of every machine cycle. If external inputs are used in counter function, then the new count appears in the registers during state 3 of the following cycle.
Shift clock makes transitions at state 3 and 6 of every machine cycle. At state 6 of every machine cycle in which 'recieve' is active, the contents of the recieve shift register are shifted to the left one position, The value that comes in from the right is the value that was sampled at state 5 of the same machine cycle.
At state 6 of every machine cycle in which 'send' is active, the contents of the transmit shift are shifted to the right position.

That's only a very small snippet of what goes on during each machine cycle.

Kai