here is code again it is only part of my whole code the whole code is around 10k not possible to understand as every body knows here i had posted only routines related to problems for explanation i repeat here again

intr0 is configered as edge triggered ,timer as mode1 16bit,intr0 rate is 10ms as interrupt arrive timer0 is loaded with delay
mov tl0,#54h ;setting1_lsb
mov th0,#0d9h ;setting1_msb
althouh delay is variable entered through keypad you can consider it fix

a,b is loaded to count how many interrupts or cycles u can say


after the delay is over timer is again looaded as given below the value to be loaded depend upon port3.1 bit before loading port3.1 is complemented it is used to generate square pulse of different high amd low time as below
isr_timer0:
setb timer_status.0
clr tcon.4
cpl port3.1
jb port3.1,pulse_high_time
mov th0,#0ffh ;low time of square pulse
mov tl0,#9ch
setb tcon.4
clr timer_status.0
reti
pulse_high_time:
mov th0,#0feh ;high time of square pulse
mov tl0,#70h
setb tcon.4
timer_return:
clr timer_status.0
reti



timer_staus.0 is status bit to record wheather the program counter was midway when it is interrpted by interrupt0 if so at return from interrupt return address is changed so that pc return to timer_return label

i think knoe u can understand





mov a,#01h ;record for how many interrupts
mob b,#10h
mov ie,#10000010b
setb tcon.0
mov tmod,#11h
setb ie.0
here:
sjmp here



interrupt0:
clr tcon.4
clr tcon.5
dec a
cjne a,#0ffh,weld_lsb_only
dec b
weld_lsb_only:
cjne a,#00h,weld_on_countinue
cjne a,b,weld_on_countinue
clr tcon.4
clr ie.0
reti
weld_on_countinue:
mov tl0,#54h ;setting1_lsb
mov th0,#0d9h ;setting1_msb
setb tcon.4
jb timer_status.0,return_in_timer
reti
return_in_timer:
mov r1,sp
mov @r1,#02h
dec r1
mov @r1,#09h ;here the flash address of label
reti ;timer_return:is loaded on stack




isr_timer0:
setb timer_status.0
clr tcon.4
cpl port3.1
jb port3.1,pulse_high_time
mov th0,#0ffh
mov tl0,#9ch
setb tcon.4
clr timer_status.0
reti
pulse_high_time:
mov th0,#0feh
mov tl0,#70h
setb tcon.4
timer_return:
clr timer_status.0
reti