??? 01/06/05 01:58 Read: times |
#84431 - ISR Responding to: ???'s previous message |
Joe Kimbriel said:
Thelam
The ISR would kick off a timer that reschedules itself and determines whether to turn the SCR on or off. They would be two independent timers, one for each ISR. Dear Joe, Thank you for your input. But in this case the ISR still has to wait for a certain amount of time until 5 pulses have completed and when it hits the RETI then it get out of there. I agree that it will use less MCU resource but timewise I think it's still the same. Let's say TM2 is used for compare and when the value is matched then Int is requested. Assuming that TM1 is preload and ready to go it just waits for the Int from CM0 to kick in. Once it kicks in, it will toggle the port pin as 5 times. When it's done then get out of the ISR. Therefore, I don't see that I can save anything here unless I change the number of pulses. In this application I have to monitor the firing angle constantly to deliver a constant current to the Motor's Field. I can't afford to miss any cycle of AC voltage line, otherwise motor will hum and creat resonance back to the transformer. I gather the actual firing time is variable therefore the two ISRs may compete if the firing times are the same or close Dear Russell Yes, the problem is worst when the firing angle of both set is the same or almost the same. Devices with a PCA would make the task siginificantly easier since the timing would be handled by the PCA hardware also since most newer parts have a 6clk or better cpu, the extra performance will also be a benefit. Yes, I thought of that as I already purchased a kit from Silabs. PS:Russell, you seem to have a lots of experience with Thyristor control don't you. If so, I hope that you wouldn't mind to share your experience with us. Thanks BTW: Thank you all for your kind inputs/suggestions. I solved my problem. I just set the IP for the CM1 higher than CM0 then everything is good. I feel better now. Regards, T.L |
Topic | Author | Date |
Optimizing ISR | 01/01/70 00:00 | |
Delay loop inside ISR=no-no | 01/01/70 00:00 | |
Delay in ISR | 01/01/70 00:00 | |
re-sched ISR | 01/01/70 00:00 | |
Timing ISR | 01/01/70 00:00 | |
ISR | 01/01/70 00:00 | |
More thoughts | 01/01/70 00:00 | |
More thought | 01/01/70 00:00 | |
how about a PCA | 01/01/70 00:00 | |
how about a PCA![]() | 01/01/70 00:00 |