I guess the demand for +-0.04° steady state error relevantly slows down the PID control, maybe due to an unsuited integral control 'Ki', unsuited in terms of allowing any fast settling.

Why not braking the cooling profile into segments working with different PID parameters, using the difference between actual temperature of probe and wished final temperature as criterium?
The first segment could use PID parameters optimized for fast settling time, still allowing much overshot and big steady state error. Then, before overshot occurs, second segment takes place, optimized for little overshot but still rather big steady state error. And finally switching to third segment, optimized for very little steady state error.

With PLL technique some similar technique is used, when very low error shall be combined with rather fast settling time. You surely remember, that across the big integration feedback resistor two antiparallel diodes are often connected then, which provide a significant reduction of integration resistance as long as the PLL system is FAR away from equilibrum. But if the equilibrum is once reached antiparallel diodes then become inactive, allowing the full intergation resistance to become active.

Kai