| ??? 01/27/01 15:19 Read: times |
#8689 - shift reg glitch revisited :) |
Hello again :)
First off, just wanted to thank those who've helped me already. Due to the suggestions I've gotten, I've cut that segment of code from around 30 lines to 8 or 9! :) Secondly, I don't know if it's considered bad ettiquitte (man, I can't spell, sorry) here to move a topic back up; If it is, let me know and I'll just drop back down to the original topic. But anyway, The prog still does exactly the same thing... Basically, I'm trying to read a bank of DIP switches that were set up by a manufacturer through a shift register. The freaks just did it wierd, though. They used the interrupt lines (Int 1 and Int 0) for the outputs (c & ps), and the Timer 0 (p3.4) line for the q8 input. Well, I got the outputs working, and have the shift register responding properly (I set up another prog to repeat the procedure over and over, and put an o-scope on it to test; it responded perfectly). The problem is that the chip isn't responding to this input. I had been using timer 0 as my primary timer (it's a very time-dependent program), so I figured that had to be the problem, and I switched over to a 89c2051 (had been using a 1051), and moved my timer over to T1. Unfortunately, it didn't help. It still reads high input at all times. The last suggestion was to set up a simple loop that checked the pin and responded with LED blinks. Did that, and it responded exactly as it had been; it kept the LED off, thus implying that it was still recieving all high (I had the LED set up to come on when output was low, which I'd guess is the most common method). I put the o-scope on it again, and had the same results; the pin was (in the real world) recieving high-lows corresponding perfectly with the DIPs; I just can't figure out why it won't recieve them... Just to add in a few new tests I've done: Since swapping the primary timer to t1, I've tried two different methods: 1, I tried moving 3.4 to c, then rrc'ing, looping this 8 times. No avail, still recieved all high bits. Then, I set up timer 0 as a counter, set the th0 and tl0 to FF, set it to interrupt on overflow, then set the interrupt to disable itself, reset the th0 and tl0 to FF, clear c, then reti. In the meantime, the program loop would set c, clock the register, enable the interrupt, then rrc. The last method is kinda stupid, I agree, but at this point, I'm trying all kinds of random BS :) Anyway, just to clear a few questions ahead of time, I am initializing 3.4 high, and I have tried it with several different chips (just to make sure that's not the problem). Help??? Anyway, thanks in advance for reading my 3-billion page essay :). I couldn't think of a quicker way to describe the problem in detail, though. If looking at my source code would help, I can post it. It's pretty long, but I can chop it down to interrupt init's, a couple of variable init's, and just this particular portion of code, and post it. As long as this is, though, I don't want to put it up unless someone asks, tho :) |
| Topic | Author | Date |
| shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| to C or not | 01/01/70 00:00 | |
RE: shift reg glitch revisited :) | 01/01/70 00:00 |



