| ??? 01/27/01 21:26 Read: times |
#8698 - RE: shift reg glitch revisited :) |
Ok, tried swapping it over to another pin, no help. So, it's definitely in the code. So, as requested, here are relevant excerpts from said code:
Just for reference, pin list: 8 P3.4 IN Q8 7 P3.3 OUT C 6 P3.2 OUT P/S First, my interrupt init variables: IEX EQU 088H IPX EQU 000H TCONX EQU 005H TMODX EQU 010H Now, my variables: DPORT EQU 090H ; CBIT EQU 3 ; PSBIT EQU 2 ; QBIT EQU 4 ; SWPORT EQU 021H DIP1: reg SWPORT.0 DIP2: reg SWPORT.1 DIP3: reg SWPORT.2 DIP4: reg SWPORT.3 DIP5: reg SWPORT.4 TBLOCK: reg SWPORT.5 EBPASS: reg SWPORT.6 SMLOCK: reg SWPORT.7 Next up, CPU init: CLR A MOV B,A mov DPTR,#0 MOV P1,#0FFH MOV P3,#0FFH MOV PSW,#PSWX MOV PCON,#PCONX MOV IE,#IEX MOV IP,#IPX MOV TCON,#TCONX MOV TMOD,#TMODX MOV TH1,#T1MSB MOV TL1,#T1LSB MOV TH0,#T0MSB MOV TL0,#T0LSB SETB TCON.6 MOV IE,#IEX Now, the actual code: MOV A,#00H clr TCON.6 clr DPORT.PSBIT setb DPORT.PSBIT SERIALA: clr c clr DPORT.CBIT setb DPORT.CBIT MOV C,DPORT.QBIT RRC A DJNZ R0,SERIALA MOV SWPORT,A setb TCON.6 Ok, that's it. Such a small portion of code to be working on for the month or so that I've been playing with it :) Oh, well, Thanks for helping me out, I really appreciate it. Oh, one more note: At first, I thought my problem might be with the SWPORT variable, since it's broken down to regs, but it all works right... If I bypass the DIP portion of code and manually set it to a value (mov swport,xxH), the rest of the program responds to that code normally. |
| Topic | Author | Date |
| shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| RE: shift reg glitch revisited :) | 01/01/70 00:00 | |
| to C or not | 01/01/70 00:00 | |
RE: shift reg glitch revisited :) | 01/01/70 00:00 |



