I do not totally agree with this statement.
If port0 pins are used as inputs, then pull-ups in this range are adequate. But if you want to emit pulses containig sharp edges by the help of port0, and if this is not done by instructions addressing external memory, then much lower pull-ups are needed!

Why?
Port0 does not turn-on strong internal active pull-ups for two oscillator periods in order to emit a low to high transition, as port1...3 does it. So, when port0 emits 'high level', then this is done by switching-off the internal open drain NMOS-FET. This makes the port0 lines float and only the presence of an external pull-up will make the line go high.

But how will this take place? Suddenly?
No. Because some stray capacitance has to be charged (capactive load at port lines) this will take some time. If pull-ups of 'R' are used and capacitive load is 'C', then rise time will be 2.2 x R x C. So, if you have a capacitve load of 50pF and a pull-up of 10kOhm, then rise time will be about 1.1µsec!

Such a rise time is totally unsuited to drive todays fast digital chips. As example, for 74HCMOS rise time must be shorter than 500nsec in order to guarantee proper performance.

But much worse: All the relevant timing specifications will no longer be valid, if the slope of low to high transitions are that undefined. Think only about the control lines to LCD display, when the positive going edges are extremely relevant.

Kai