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???
03/21/05 06:40
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#90076 - re:Pull-ups, used at outputs or inputs?
Responding to: ???'s previous message
Dear Kai,
Thanks for your valuable answer,
Mehdi said:
If this step qualified then
the resistors between 5.6k,10k are typical for P0 pullups.

Kai said:

I do not totally agree with this statement.
If port0 pins are used as inputs, then pull-ups in this range are adequate.

I say typical and i dont say complete
why you say { inputs }?you can use 5.6k-10k pullups res
as output.
the sentence below was very useful
Kai said:


if you want to emit pulses containig sharp edges by the help of port0, and if this is not done by instructions addressing external memory, then much lower pull-ups are needed!

Why?

Port0 does not turn-on strong internal active pull-ups for two oscillator periods in order to emit a low to high transition, as port1...3 does it. So, when port0 emits 'high level', then this is done by switching-off the internal open drain NMOS-FET. This makes the port0 lines float and only the presence of an external pull-up will make the line go high.


What is proper performance in the following sentence?
Kai said:

rise time will be about 1.1µsec!
Such a rise time is totally unsuited to drive todays fast digital chips. As example, for 74HCMOS rise time must be shorter than 500nsec in order to guarantee proper performance.


Thanks again for your time which give us.
Mehdi


List of 6 messages in thread
TopicAuthorDate
Problems with Port 0            01/01/70 00:00      
   Pull-ups too high - use another port            01/01/70 00:00      
   Pullups            01/01/70 00:00      
   To jay!            01/01/70 00:00      
      Pull-ups, used at outputs or inputs?            01/01/70 00:00      
         re:Pull-ups, used at outputs or inputs?            01/01/70 00:00      

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