Dear Micheal,
Both 89C52 and 89C51RD2 are operating on 11.0592MHZ. RD2 is operating on normal mode( not in X2 clk mode).The SPI is configures for Fclk/128 thats the slowest speed with CPHA and CPOL as high, means the SPI clk will be idle high and data will flow out of AT89C51RD2 with low to high transitions of SPI clk and will flow in with high to low transitions of SPI clk. Further the ADC AD7730 is "getting initialised" in continuous read mode. Accordingly the POL pin is set to high. More the ADC arrangement remains the same when 89C52 / 89C51RD2 is interfaced.

Now how can we determine the data rate of the ADC chip because in the data sheet, it shows a standard interface with MC68HC11 uc
which is having the same SPI clk rates as AT89C51RD2. ADC is suposed to give us 50 conv/sec.

We have put pull up resistors across SPI port of RD2 and dissabled the weak pull ups inside RD2. Can you throw some light on pushpull io pins and quasi bidirectional io pins.

Whenever the ADC finishes the conversion it will set the RDY line low interrupting the RD2. it is behaving in the same fashion with 89C52, so it works well there.

thanx a ton for your replies members.

Micheal i will be waiting for your reply.

Regards
Sushant