AT89C51RD2 data sheet Page 67:
1. The SPI Module should be configured as a Master before it is enabled (SPEN set).
...
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
Does it mean instead of
MOV SPCON,#01110001B;Master with SS disabled @ f/4=2.7648MHz(2.8935us per byte)
Where SPI configuration is done in the same MOV which enables the SPI,
we should use(Notice bit 6)
MOV SPCON,#00110001B;Master with SS disabled @ f/4=2.7648MHz(2.8935us per byte)
MOV SPCON,#01110001B;Enable SPI (SPEN set) after setting MSTR, CPOL and CPHA bits
Where bit 7 is 'manually' set in a second MOV instruction?(looks rather eccentric)