| ??? 08/02/05 09:25 Read: times |
#98660 - SPI and Interprocessor communication |
Hello,
1. I have connected a LPC932 ( Slave) to a P89LV51RD2BA (Master). The connections are as follows MISO - MISO, MOSI - MOSI, SPICLK - SPICLK, P1.4(LV51) is tied HI, and P2.4(LPC) is held LO by LV51 thru P1.1(LV51). The LPC has internal Oscillator selected( 7.373 MHz), while the LV51 is 6CLK @ 11.05992 MHz. 2. When I transmit a byte from the LV51 the LPC receives it with the LSB at LO, that is to say only the top 7 bits are received correctly. 3. The control word for LV51 is SPCR = 0x5D; and that for LPC is SPCTL = 0x4C; 4. a) I have tried using a common clock for LV51 and LPC but no effect. b) Similarly changing transmit frequency from f/16 thru f /128 has no effect, however it does not work for f/4. c) Shorting MISO to MOSI of LV51 works perfectly for transmit and readback. Since the LPC is configured for SPI it ought to send back what it received, as it is supposed to work like a 8 bit Shift register.It does so but with an erroneous LSB. If any of you have faced a similar issue please reply. Regards Pramod |
| Topic | Author | Date |
| SPI and Interprocessor communication | 01/01/70 00:00 | |
| Is it possible | 01/01/70 00:00 | |
| SPI Master/Slave | 01/01/70 00:00 | |
| You answered Yes, the Slave thus | 01/01/70 00:00 | |
| SPI Connections | 01/01/70 00:00 | |
| I know what it stands for, but do not kn | 01/01/70 00:00 | |
| SPI pins | 01/01/70 00:00 | |
| not a good base for a design | 01/01/70 00:00 | |
| closer look | 01/01/70 00:00 | |
no success | 01/01/70 00:00 |