| ??? 08/03/05 12:36 Read: times |
#98745 - closer look Responding to: ???'s previous message |
Hello Erik,
I have now cut-pasted from the user manual. • SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on the MOSI (Master Out Slave In) pin and flows from slave to master on the MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions. Only the SPICLK switches direction. Thanks to you I have given the manual a closer look once more, and the snippet below looks promising. MOSI and SPICLK are at high impedance to avoid bus contention when the MAster is idle. The application must pull-up or pulldown SPICLK (depending on CPOL- SPCTL.3) to avoid a floating SPICLK. Regards Pramod |
| Topic | Author | Date |
| SPI and Interprocessor communication | 01/01/70 00:00 | |
| Is it possible | 01/01/70 00:00 | |
| SPI Master/Slave | 01/01/70 00:00 | |
| You answered Yes, the Slave thus | 01/01/70 00:00 | |
| SPI Connections | 01/01/70 00:00 | |
| I know what it stands for, but do not kn | 01/01/70 00:00 | |
| SPI pins | 01/01/70 00:00 | |
| not a good base for a design | 01/01/70 00:00 | |
| closer look | 01/01/70 00:00 | |
no success | 01/01/70 00:00 |