??? 08/02/05 17:42 Read: times |
#98708 - SPI Master/Slave Responding to: ???'s previous message |
Tht master/slave devices always (even in slave mode) output on MOSI ?.
Yes, the Slave thus shifts out what it had previously received in its Buffer or written anew by the Slave routine. So we get an echo of data with a byte lag. We effectively have a 16 bit shift register (8bits in Master & 8 in Slave). What's a nugget switch? Pramod |
Topic | Author | Date |
SPI and Interprocessor communication | 01/01/70 00:00 | |
Is it possible | 01/01/70 00:00 | |
SPI Master/Slave | 01/01/70 00:00 | |
You answered Yes, the Slave thus | 01/01/70 00:00 | |
SPI Connections | 01/01/70 00:00 | |
I know what it stands for, but do not kn | 01/01/70 00:00 | |
SPI pins | 01/01/70 00:00 | |
not a good base for a design | 01/01/70 00:00 | |
closer look | 01/01/70 00:00 | |
no success![]() | 01/01/70 00:00 |