| ??? 09/01/05 16:57 Modified: 09/01/05 16:59 Read: times |
#100422 - a latch is not a flip flop, when the gat Responding to: ???'s previous message |
a latch is not a flip flop, when the gate is open (in your case STROBE is high) data flow freely from the input to the output, when the gate is closed (in your case STROBE is low)there is no connection. Thus data is latched whenever the gate is closed. Thus the time data is latched is when the gate closes (in your case "on the negative edge of the STROBE") and it will stay the same till the gate is opened.
Erik |
| Topic | Author | Date |
| CD4094BC | 01/01/70 00:00 | |
| a latch is not a flip flop, when the gat | 01/01/70 00:00 | |
| May I add... | 01/01/70 00:00 | |
| CD4094BC | 01/01/70 00:00 | |
| Synchronous and asynchronous operation | 01/01/70 00:00 | |
| 8 bit shift register, 8 bit parallel out | 01/01/70 00:00 | |
Thank You | 01/01/70 00:00 |