| ??? 09/01/05 17:36 Read: times |
#100424 - May I add... Responding to: ???'s previous message |
Erik said:
a latch is not a flip flop, when the gate is open (in your case STROBE is high) data flow freely from the input to the output, when the gate is closed (in your case STROBE is low)there is no connection. Thus data is latched whenever the gate is closed. Thus the time data is latched is when the gate closes (in your case "on the negative edge of the STROBE") and it will stay the same till the gate is opened. So, Sudheer, keep the STROBE input logic low during shift operations. When all the shifting is done, means after stopping any activity at CLOCK input, then pulse the STROBE input high for a short period: The low to high toggle will make the latch becoming "transparent", means the output will show a copy of stored data in shift register. The high to low toggle, just afterwards, will keep the actualized outputs latched. So, the outputs become actualized with the low to high edge at STROBE input. Kai |
| Topic | Author | Date |
| CD4094BC | 01/01/70 00:00 | |
| a latch is not a flip flop, when the gat | 01/01/70 00:00 | |
| May I add... | 01/01/70 00:00 | |
| CD4094BC | 01/01/70 00:00 | |
| Synchronous and asynchronous operation | 01/01/70 00:00 | |
| 8 bit shift register, 8 bit parallel out | 01/01/70 00:00 | |
Thank You | 01/01/70 00:00 |