This is stupid. Okay, I admit that up front. I always knew you could interface external sram chips to the 8051, but I never really gave it any thought until using the SBC. Well, I was wondering how is it possible for the 8051 to access the external sram and still use those lines as general IO pins.
At first I thought it couldn't be done (both at the same time), then I thought there had to be a line from the 8051 to enable sram access. Reading the datasheet for my 420/430, it says on one line that "If Ports 0/2 are used for external memory, they cannot be used as I/O lines." However, there is another section that says something else, basically stating that if external program store (eeprom) is used, they cannot be used as IO lines; and later, when reading abount the PSEN/RD/WR lines, it looks to me as if the SRAM chip itself (as if only storing data to it, and not running a program off of it) would either tell the sram chip to ignore the port lines or listen to them while reading or writing.

I think this is a case where my own self having overanalysed everything, has made it ten times more complex than it can be.

So, my questions are this :
1. Can a program (being written and stored on the 8051 itself) access external SRAM to store data, but still use ports 0,2 for general purpose I/O?
2. Is there a line (psen?) which is enabled while writing or reading from the sram chip?
3. Assuming there is on #2, if this line is not active, can pins on the port connected to the sram chip be set (setb P0.5, for example) without the sram data being altered?

Help, I've confused the crap out of myself again. lol