Whenever a CMOS totem pole switches, there's a very short interval during both the upper and lower transistors of the totem pole are "on." That's what causes most of the noise, and the power consumption in CMOS logic. Now, it's not going to happen for tens of nanoseconds, let alone microseconds, or milliseconds, as would a keyswitch closure, if you scan the array properly, i.e. write the row sink bit, read the columns, then release the row-sink, you'll get the proper reading if you've timed things properly, yet you won't exceed the short-circuit current limit for those pins, even if there is a multi-key closure.

MOSFETs aren't a dead short when turned on, and, in fact, that's the main weakness they exhibit. They're a resistor, in essence, the characteristics of which depend mostly on what the manufacturer has done when designing the part. The reason the output voltage, when "high," drops as the load increases is because it's behaving as a resistor. The reason the output voltage rises when low, is similar. The voltage offset across the mosfet is low when the current is low. The power dissipation is low when the current is low. During those ultra-short intervals when both members of the CMOS totem pole are active, they're both conducting. That's a major source of noise and heating in CMOS, but it shouldn't be a concern if there are two connected totem poles both of which are, in fact, limited in their current by internal resistors placed there for that explicit purpose. Moreover, if you only have this condition for a few microseconds, you won't damage anything because it is well with in worst-case limits.

Now I wouldn't recommend designing a circuit based on the limits that the characteristic resistances in the CMOS totem pole provides, but it's clear that it should be more than adequate protection against the circumstance you suggest as potentially harmful.

I've had CMOS high-to-low connection inadvertently left powered-on overnight on the lab bench many times over the past 30+ years, and not once seen a device failure as a result. They do get warm, and one shouldn't do that, but, unless the device limits or the pin limits on power dissipation are exceeded, there's no reason to fear.

RE