In your program, timer 0 overflows every 256 usec (using a 12 MHx clock). However, the ISR (who really toggles the output pin) might be executed at less precise intervals because of latency.
That is, the time elapsed since timer 0 overflows until cpl px.y is executed can vary slightly depending on what instruction is being executed when the timer overflows.
In other words, there are a minimum and a maximum latency times, but not a fixed one.
Even so, the long term frequency in the output pin will be very stable, the only problem is that some half-cycles will be slightly different from others. This could be important or not depending on the specific application.

Alfredo.