| ??? 01/25/07 19:30 Read: times |
#131486 - hmmm..... Responding to: ???'s previous message |
Erik and Lynn,
Thanks for the info... The state of the I/O pin is tied high externally...let's even go as far as to say it's directly attached to an external power supply (it's not, but you get the picture...). That being said even if the 8051 resets, the signal stays high. So I think that rules out your explanation, Erik (though I should have pointed out that the external signal is always high...). Lynn, could you elaborate on the hardware bug (if you're allowed to)? Thanks! D |
| Topic | Author | Date |
| External Interrupt triggering on initialization | 01/01/70 00:00 | |
| Simple! | 01/01/70 00:00 | |
| yes, but..... | 01/01/70 00:00 | |
| There's probably a good reason. | 01/01/70 00:00 | |
| worth a shot...but | 01/01/70 00:00 | |
| Understanding interrupts | 01/01/70 00:00 | |
| Yes, I Know | 01/01/70 00:00 | |
| terse response | 01/01/70 00:00 | |
| tried clr IE0... | 01/01/70 00:00 | |
| clr IE ?? | 01/01/70 00:00 | |
| I do not use the SILabs deviates, but | 01/01/70 00:00 | |
| Interesting.... | 01/01/70 00:00 | |
| AH, now we get a good guess at the reason. The ex | 01/01/70 00:00 | |
| Maybe it is the part | 01/01/70 00:00 | |
| are you sure | 01/01/70 00:00 | |
| hmmm..... | 01/01/70 00:00 | |
| Hardware bug | 01/01/70 00:00 | |
| down memory lane | 01/01/70 00:00 | |
INT0 is assigned to P0.1 as the default | 01/01/70 00:00 |