Detecting of tristate condition seems to be rather simple, but is not! Ok, you can detect a potential, that is neither low nor high, but you still don't know, whether this is the consequence of a high-Z state of tristate output or just the consequence of a toggle from low to high or high to low.

Also, a high-Z state of a tristate output does not necessarily mean, that the potential automatically is in the nowhere's land, means is neither high nor low.

So, first we should add a biasing network, that forces the potential to drift to the nowheres's land, when the tristate output is in high-Z state. Here the first problem arises. What is neither high nor low in a TTL system can be a valid level in a CMOS system! And vice versa. So, addding a biasing network will only work, if we know what kind of logic will emit the high-Z state.

But even if we know, what kind of logic is used, how to find out, that the wrong potential isn't simply the cause of a regular edge due to toggling from high to low or vice versa? A window comparator will detect the "wrong" potential, but not answer this question.

What is still needed is an interpretation of the window comparator's output, an analysis of how long the wrong potential lasts. But again problems arise: What is the regular slew rate of a digital signal? How will the unpredictable stray capacitance affect this slew rate and, of special interest, the settling time of biasing network?

So, detection of high-Z state of a tristate output is a rather complex task. I think the best approach would be the use of an ultra fast ADC to get a proper copy of the signal shape and then doing some interpretation of the many samples.

Kai