Peter,

The board's manual comes with a table expressing the memory map.

For application run time:
CE0: 00000-7FFFF, code page 0
CE1: 80000-FFFFF, code page 1
CE2: unused,
CE3: unused.
PCE0:00000-7FFFF, data page 0
PCE1:80000-FFFFF, data page 1
PCE2:80000-FFFFF, 4KB Mem. Map I/O
PCE3:EPROM enable I/O bit
----:400000-4011FF - 4KB On-Chip SRAM data/code

For their loader run time:
CE0: 00000-7FFFF, - 32K EPROM / 512K data
CE1: 80000-FFFFF, - code page 1
CE2: unused,
CE3: unused.
PCE0:00000-7FFFF, - data page 0 (not when code page 0 is accessed)
PCE1:80000-FFFFF, - data page 1
PCE2:80000-FFFFF - 4KB Mem. Map I/O
PCE3:EPROM enable I/O bit
----:400000-4011FF - 4KB On-Chip SRAM

There is also a note which indicates that their loader/interpreter copies a
small loader to the on chip SRAM (which can be overlaid data/code) and this
chunk of code does the RAM loading from the serial port. I suppose I'll need
to do something similar. I think the advantage to this is the on-chip SRAM
is mapped into space which does not conflict with any possible destination
addresses.

It seems they have two ways of enabling the EPROM, CE0 and PCE3. I'm not
sure exactly what this means. As I understand it, the PCE's are active for
data access and CE's are active for code access. I'm not sure of the easiest
way to use this setup. I know I have to map the destination code space for
my application as data to copy it there. I also need to either map the EPROM
as data, or read it with MOVC instructions (right?). Maybe the PCE3 signal
can be used to read from the EPROM. It would exist at 100000-107FFF in this
case (I believe). If this can be done, then the destination code space for
my application could be 0000-7FFF and beyond, overlapping where the EPROM
exists in code space.

Again it is now time for me to dig into the 80390 user's guide and figure
out how to address locations as large as 400FFF, and how to map overlay
code and data space.

Thanks for all your help,

-Rick