The 8051 and PIC implements separate internal program and data busses.

The 8051 accesses the different memory areas sequentially during different nt clock "phases" of each machine cycle, hence the 12X clock to machine cycle ration of the std. 8051. The new DS89C420 still does this just with fewer clocks.

The PIC access occurs simulataneously so i agree with Alfredo that the PIC is a closer implementation of Aiken architecture. (for what thats worth, as the PIC is pain to work with).

The Analog Devices ADSP series is an even better example where you will see the simultaneous access to program and data memory occur even when either of the two maps are external to the chip. The original ADSP2100 would simultaneously access both maps off chip (like a MIPS processor).