Phillip,

I agree, DSPs are a good example of Harvard architecture.

Only one additional comment.
In the first paragraph you say that "the 8051 inplements separate program and data buses".
However, in the original 8051 block diagram from Intel, I see an internal shared 8-bit data bus where both the ROM and the RAM send their outputs. Though, of course, each memory has its own address bus.

In the second paragraph you indicate that "the 8051 accesses the different memory areas sequentially during different clock phases".
I think that the 8051 has to do it this way, because there is only one shared data bus.

Regards,

Alfredo del Rio.