Alfredo,

I stand corrected, you are right. All the 8051 and variants i've just revued (51/52/ 89C51/2, i251, ds320/ds5000) implement a single 8 bit bus for data and program access. Thus, as you correctly noted, the sequentiality of access to these memory maps within the 8051 machine cycle phases.

The PIC is certainly a better example of the Aiken architecture, (again for what it's worth).

Your PIC analysis reveals the assymetry of the program "word" width and the data "word" width. This is again a capability/characteristic of the Aiken architecture. (With the benefit of longer instruction word lengths potentially eliminating the requirement for micro-code).

Bordyn,

Other than the requirement to "view" and access the different Maps why would you say the Aiken architecture is harder to debug(or did you mean the specific example you were confronted with)?

regards,
p